1. Field of the Invention
The present application relates to a thin film transistor, and more particularly, to a polycrystalline silicon thin film transistor for a display device and a method of fabricating the polycrystalline silicon thin film transistor.
2. Discussion of the Related Art
Recently, as interest in information displays and demand for portable information media increase, flat panel displays (FPDs) have been the subject of research and commercialization in substitution for cathode ray tube (CRT) display devices. Among various FPDs, active matrix liquid crystal display (AM-LCD) devices having light weight, thin profile and low power consumption have been widely used for notebooks and monitors because of their superiority in display quality. The AM-LCD device includes a plurality of pixel regions each having a thin film transistor as a switching element to control a voltage to be applied to a liquid crystal layer of each pixel region, thereby changing transmittance of corresponding pixel region.
A liquid crystal display (LCD) device includes a liquid crystal panel to display images and a driving unit to supply signals to the liquid crystal panel. The liquid crystal panel includes two substrates facing each other and spaced apart from each other with a liquid crystal layer between the two substrates. The two substrates are usually referred to as an array substrate and a color filter substrate, respectively. The array substrate includes a plurality of gate lines parallel to and spaced apart from each other, a plurality of data lines crossing the plurality of gate lines to define a plurality of pixel regions, a plurality of thin film transistors (TFTs) each connected to each gate line and each data line, and a plurality of pixel electrodes each connected to a respective TFT.
The TFT used as a switching element of an LCD device may be classified into an amorphous silicon type and a polycrystalline silicon type according to a phase state of the active layer. Since carrier mobility of a TFT using polycrystalline silicon as an active layer is ten to one hundred times greater than that of a TFT using amorphous silicon as an active layer, a driving circuit including the polycrystalline silicon TFTs is typically used. Thus, the polycrystalline silicon TFT will be used as a switching element and a driving element for a display panel of next generation having high resolution.
In addition, the polycrystalline silicon TFT may be applied to an organic electroluminescent display (OELD) device, which is alternatively referred to as an organic light emitting diode (OLED) device, as a switching element. The OELD device includes first and second electrodes and an emitting layer between the first and second electrodes. Electrons and holes are injected into the emitting layer from the first and second electrodes, respectively, and the emitting layer emits light when excitons generated from combination of the electrons and the holes are transited from an excited state to a ground state. Since the emissive type OELD device does not require an additional light source, the OELD device has reduced volume and weight.
FIGS. 1A to 1D are cross-sectional views showing a method of fabricating a thin film transistor according to the related art. In FIG. 1A, a buffer layer 20 is formed on a substrate 10 having a pixel region PA. The pixel region PA, which is a unit for displaying images, includes a switching area SA for a thin film transistor (TFT) and the switching area SA includes a semiconductor area BA for an active layer. The semiconductor area BA includes a source area S, a drain area D and a channel area C. The buffer layer 20 includes an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx). Next, after an amorphous silicon layer (not shown) is formed on the buffer layer 20 using a plasma chemical vapor deposition (PCVD) method, the amorphous silicon layer is crystallized to be a polycrystalline silicon and the polycrystalline silicon is patterned to be an active layer 40 in the semiconductor area BA. The buffer layer 20 prevents contamination of the active layer 40 due to impurities from the substrate 10 during the deposition and crystallization steps. The amorphous silicon layer may be crystallized using one of excimer laser annealing (ELA) method, a solid phase crystallization (SPC) method, a sequential lateral solidification (SLS) method, a metal induced crystallization (MIC) method and an alternative magnetic lateral crystallization (AMLC) method.
In FIG. 1B, a gate insulating layer 45 is formed on the active layer 40. The gate insulating layer 45 includes an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx). Next, a gate electrode 25 and a gate line (not shown) are formed on the gate insulating layer 45 by depositing and patterning one of copper (Cu), molybdenum (Mo), aluminum (Al) and aluminum alloy. The gate electrode 25 is connected to the gate line and corresponds to the active layer 40, and a gate signal is applied to the gate electrode 25 through the gate line.
Although not shown in FIG. 1B, the active layer 40 corresponding to the source and drain areas S and D is doped with impurities having a negative type or a positive type using the gate electrode 25 as a doping mask to become a semiconductor layer 42. As a result, the semiconductor layer 42 includes a channel region 42a that does not have the impurities and first and second doped regions 42b and 42c having the impurities. The channel region 42a corresponds to the gate electrode 25 and the first and second doped regions 42b and 42c are disposed at both sides of the channel region 42a. Next, a passivation layer 55 is formed on the gate electrode 25 by depositing one of an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx), and an organic insulating material, such as photo acryl or benzocyclobutene (BCB).
In FIG. 1C, the passivation layer 55 and the gate insulating layer 45 are patterned to form a source hole SH and a drain hole DH exposing the semiconductor layer 42 corresponding to the source region S and the drain region D, respectively.
In FIG. 1D, a data line (not shown), a source electrode 32 and a drain electrode 34 are formed on the passivation layer 55. The data line crosses the gate line to define the pixel region PA. The source electrode 32 extends from the data line and the drain electrode 34 is spaced apart from the source electrode 32. The source and drain electrodes 32 and 34 are connected to the semiconductor layer 42 through the source and drain holes SH and DH, respectively. Next, an interlayer insulating layer 65 is formed on the data line, the source electrode 32 and the drain electrode 34. The interlayer insulating layer 65 has a drain contact hole DCH exposing the drain electrode 34. The interlayer insulating layer 65 includes one of an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx), and an organic insulating material, such as photo acryl or benzocyclobutene (BCB). Next, a pixel electrode 70 is formed on the interlayer insulating layer 65 in the pixel region PA. The pixel electrode 70 is connected to the drain electrode 34 through the drain contact hole DCH.
FIGS. 2A to 2D are cross-sectional views showing steps of forming an active layer and a gate insulating layer of FIGS. 1A and 1B for a thin film transistor according to the related art. In FIG. 2A, after an amorphous silicon layer (not shown) is formed on a buffer layer 20 by depositing amorphous silicon (a-Si:H) using a chemical vapor deposition (CVD) method, the amorphous silicon layer is crystallized to become a polycrystalline silicon layer 40a. Next, a photoresist (PR) layer 60 is formed on the polycrystalline silicon layer 40a and a photo mask M having a blocking portion T1 and a transmissive portion T2 is disposed over the PR layer 60. The blocking portion T1 is aligned to correspond to the semiconductor area BA and the transmissive portion T2 is aligned to correspond to the other areas. Since the blocking portion T1 shields light of an exposing apparatus (not shown) over the photo mask M and the transmissive portion T2 transmits the light, the PR layer 60 corresponding to the blocking portion T1 is not exposed to the light and the PR layer 60 corresponding to the transmissive portion T2 is exposed to the light to have a chemical transition.
In FIG. 2B, the light of the exposing apparatus is irradiated onto the PR layer 60 through the photo mask M to form a PR pattern 62 corresponding to the semiconductor area BA. Next, the polycrystalline silicon layer 40a is patterned using the PR pattern 62 as an etch mask by a dry etch method. For example, the polycrystalline silicon layer 40a may be etched by a plasma dry etch method using reaction gases, such as sulfur hexafluoride (SF6), chlorine (Cl2) and argon (Ar). During the dry etch step, the PR pattern 62, the polycrystalline silicon layer 40a and the buffer layer 20 have different etch rates for the reaction gases of sulfur hexafluoride (SF6), chlorine (Cl2), and argon (Ar). The PR pattern 62 and the buffer layer 20 have a first etch rate, and the polycrystalline silicon layer 40a has a second etch rate greater than the first etch rate. As a result, the PR pattern 62 and the buffer layer 20 are slowly etched, and the polycrystalline silicon layer 40a is quickly etched. Accordingly, deteriorations, such as an under etch phenomenon of the polycrystalline silicon layer 40a and an over etch phenomenon of the buffer layer 20, are prevented.
In FIG. 2C, the polycrystalline silicon layer 40a (of FIG. 2B) exposed through the PR pattern 62 is removed to form an active layer 40 having an island shape. Since the second etch rate of the polycrystalline silicon layer 40a for the reaction gases of sulfur hexafluoride (SF6), chlorine (Cl2) and argon (Ar) is relatively high, upper and lower portions of the polycrystalline silicon layer 40a adjacent to the PR pattern 62 are nearly completely removed and the active layer 40 has edge portions of a taper shape having a relatively steep slope instead of a relatively slow slope. For example, a taper angle θ, which a step coverage of a subsequent gate insulating layer 45 (of FIG. 1B) depends on, between side and bottom surfaces of the active layer 40 may be equal to or greater than about 80° (θ≧80°).
In FIG. 2D, a gate insulating layer 45 of an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx), is formed on an entire surface of the substrate 10 having the buffer layer 20 and the active layer 40 by a plasma chemical vapor deposition (PCVD) method using reaction gases such as mono silane (SiH4) or tetraethylorthosilicate (TEOS). The TEOS has advantages such as harmlessness to human, easy handling and excellent chemical stability. As the step coverage of the gate insulating layer 45 at edge portions of the active layer 40 is improved, a breakdown voltage of the gate insulating layer 45 increases and a leakage current of the gate insulating layer 45 decreases. In addition, an electric property of the TFT depends on the breakdown voltage and the leakage current of the gate insulating layer 45. As a result, it is required for improved step coverage of the gate insulating layer 45 and an improved electric property of the TFT that the active layer 40 should have edge portions of a taper shape having a relatively slow slope.
Recently, as a degree of integration increases, the thickness of the active layer 40 has decreased to be about 300 Angstroms (Å). In addition, as the thickness of the active layer 40 is reduced, it is more difficult to form the active layer 40 having edge portions of a taper shape having a relatively slow slope. When the gate insulating layer 45 is formed on the active layer 40 having the taper angle θ equal to or greater than about 80 degrees, the gate insulating layer 45 may have deteriorations such as a crack at step difference portions F and G corresponding to the edge portions of the active layer 40. Further, since the breakdown voltage is reduced and the leakage current increases, reliability of the TFT is degraded.
FIG. 3 is a cross-sectional image showing an active layer and a gate insulating layer for a thin film transistor according to the related art. In FIG. 3, when a gate insulating layer 45 is formed on an active layer 40 by a plasma chemical vapor deposition (PCVD) method using tetraethylorthosilicate (TEOS), the gate insulating layer 45 has a bottom thickness Tb corresponding to a buffer layer 20, a top thickness Tt corresponding to a top portion of the active layer 40 and a side thickness Ts corresponding to an edge portion of the active layer 40. The bottom thickness Tb is substantially the same as the top thickness Tt (Tb/Tt≈0.99), and the side thickness Ts is substantially a half of the top thickness Tt (Ts/Tt≈0.52). When the gate insulating layer 45 is formed by a PCVD using mono silane (SiH4), ratios of the bottom thickness Tb to the top thickness Tt and the side thickness Ts to the top thickness Tt are about 0.99 and about 0.75, respectively. (Tb/Tt≈0.99, Ts/Tt≈0.75) For example, when each of the bottom and top thicknesses Tb and Tt of the gate insulating layer 45 is about 500 Angstroms (Å), the side thickness Ts of the gate insulating layer 45 may be within a range of about 240 Angstroms (Å) to about 380 Angstroms (Å) due to a poor step coverage at the edge portion of the active layer 40. As a result, the gate insulating layer 45 may have a crack at step difference portions corresponding to the edge portion of the active layer 40, and the breakdown voltage and the leakage current of the TFT is degraded.
To improve the step coverage of the gate insulating layer 45 at the step difference portions thereof, the active layer 40 must have a tapered shape within a relatively slow slope at the edge portion thereof. However, since the thickness of the active layer is reduced to about 300 Angstroms (Å) to about 500 Angstroms (Å), limitations exist in obtaining a taper shape with a relatively slow slope.